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Download Alpha Architecture Reference Manual by Alpha Architecture Committee, Richard T. Witek PDF

By Alpha Architecture Committee, Richard T. Witek

This can be the authoritative reference on electronic apparatus Corporation's new 64-bit RISC Alpha structure. Written via the designers of the interior electronic standards, this publication includes entire descriptions of the typical structure required for all implementations and the interfaces required to aid the OSF/1 and OpenVMS working systems.

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Ab" m e a n s t h e o p e r a n d is already in byte u n i t s (used in load/store instructions). 3-4 i The o p e r a n d is a n i m m e d i a t e literal in t h e instruction. r T h e operand is r e a d only. m The operand is both r e a d a n d w r i t t e n . Common Architecture (I) Access Type Meaning w T h e o p e r a n d is w r i t e only. 3 Operators The operators shown in Table 3 - 4 a r e used: Table 3-4: Operators Operator Meaning ! ): Operators Operator Meaning x M'thbit of χ ACCESS(x,y) Accessibility of the location whose address is χ using the access mode y.

2. No operator precedence is a s s u m e d o t h e r t h a n t h a t r e p l a c e m e n t (<-) h a s t h e lowest precedence. Explicit precedence is indicated by t h e u s e of "{}". 3. All arithmetic, logical, a n d relational operators a r e defined in t h e context of t h e i r operands. For example, "+" applied to G_floating o p e r a n d s m e a n s a G_floating add, w h e r e a s "+" applied to q u a d w o r d o p e r a n d s is a n integer add. Similarly, "LT" is a G_floating comparison w h e n applied to G_floating o p e r a n d s a n d a n integer comparison w h e n applied to quadword o p e r a n d s .

If t h e per-processor lock_flag is (still) set w h e n a STx_C instruction is executed, t h e store occurs; otherwise, it does not occur, a s described for t h e STx_C instructions. If processor A's lock_flag is set a n d processor Β successfully does a store w i t h i n A's locked r a n g e of physical addresses, t h e n A's lock_flag is cleared. A processor's locked 4-8 Common Architecture (I) r a n g e is t h e aligned block of 2**N bytes t h a t includes t h e locked_physical_address. T h e 2**N value is i m p l e m e n t a t i o n d e p e n d e n t .

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